The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 24, 2015

Filed:

Oct. 30, 2013
Applicant:

Massachusetts Institutes of Technology, Cambridge, MA (US);

Inventors:

Arash Akhavan Fomani, Melrose, MA (US);

Luis Fernando Velasquez-Garcia, Newton, MA (US);

Akintunde Ibitayo Akinwande, Newton, MA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01J 9/02 (2006.01); H01J 1/304 (2006.01); H01L 21/00 (2006.01);
U.S. Cl.
CPC ...
H01J 9/025 (2013.01); H01J 1/304 (2013.01); H01L 21/00 (2013.01);
Abstract

Methods for fabrication of self-aligned gated tip arrays are described. The methods are performed on a multilayer structure that includes a substrate, an intermediate layer that includes a dielectric material disposed over at least a portion of the substrate, and at least one gate electrode layer disposed over at least a portion of the intermediate layer. The method includes forming a via through at least a portion of the at least one gate electrode layer. The via through the at least one gate electrode layer defines a gate aperture. The method also includes etching at least a portion of the intermediate layer proximate to the gate aperture such that an emitter structure at least partially surrounded by a trench is formed in the multilayer structure.


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