Dynamic data dimensioning by partial reconfiguration of single or multiple field-programmable gate arrays using bootstraps

Abstract

An approach is presented for managing resources of a field-programmable gate array (FPGA). At runtime, first data is extracted and processed. At runtime and via a very high speed integrated circuit hardware description language (VHDL) interface, a change in a size, a structure, or a load schedule of next data is received. The change is determined by a quantitative method analyzing the first data and executing external to the FPGA. At runtime, a first bootstrap code in the FPGA executes, and in response, other bootstrap codes in the FPGA are updated. The first bootstrap code is configured to update the structure of the next data. The other bootstrap codes are configured to extract and process, and to determine an order of processing and a configuration of the next data. The next data is extracted and processed based on the updated other bootstrap codes.