The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 24, 2015
Filed:
Dec. 20, 2011
Applicants:
Sean S. Chen, Sunnyvale, CA (US);
Liwei Liu, San Jose, CA (US);
Yongliang Wang, Saratoga, CA (US);
Inventors:
Assignee:
Atmel Corporation, San Jose, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G05F 1/56 (2006.01); G05F 1/575 (2006.01);
U.S. Cl.
CPC ...
G05F 1/575 (2013.01);
Abstract
An adaptive phase-lead compensation (zero) circuit is disclosed that can be added to a circuit (e.g., a CMOS-based LDO) to ease the compensation and increase the phase margin of the circuit. By using the disclosed adaptive phase-lead compensation circuit, an adjustable resistance can be connected to any nodes in the compensated circuit rather than just to the voltage source (VDD) or ground (GND), allowing the Miller Effect to be used via a Miller capacitor.