Control test point for timing stability during scan capture

Abstract

A control test point (CTP) of an integrated circuit scan chain includes a scan latch and an integrated clock gate (ICG). The ICG includes clock, functional enable (FE) and scan enable (SE) inputs, and a gated clock output. The ICG can respond to an SE input active state, in a serial scan mode allowing the gated clock output to change. The ICG can also be operated in a scan capture mode, responding to an SE input inactive state, in which the gated clock output is inhibited from changing in response to a low FE input level. The ICG's gated clock output is coupled to the scan latch clock input, which holds its data output at a fixed level in response to ICG's gated clock output being inhibited from changing during the scan capture operation.