The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 17, 2015

Filed:

Apr. 04, 2014
Applicant:

Samsung Electronics Co., Ltd., Suwon-Si, Gyeonggi-Do, KR;

Inventors:

Yoon-Hae Kim, Suwon-si, KR;

Hwa-Sung Rhee, Seongnam-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 27/01 (2006.01); H01L 23/522 (2006.01); H01L 49/02 (2006.01); H01L 21/768 (2006.01); H01L 27/108 (2006.01);
U.S. Cl.
CPC ...
H01L 27/016 (2013.01); H01L 23/5223 (2013.01); H01L 23/5228 (2013.01); H01L 28/20 (2013.01); H01L 28/60 (2013.01); H01L 21/76879 (2013.01); H01L 27/10852 (2013.01); H01L 27/10858 (2013.01); H01L 27/10861 (2013.01);
Abstract

A semiconductor device includes an interlayer dielectric layer on a substrate, the interlayer dielectric layer having an upper surface, a lower plug extending down into the interlayer dielectric layer from the upper surface of the interlayer dielectric layer, the lower plug having an upper surface, a first dielectric layer pattern on the upper surface of the lower plug, at least a portion of the first dielectric layer pattern being directly connected to the upper surface of the lower plug, a first metal electrode pattern on the first dielectric layer pattern, a first upper plug electrically connected to the first metal electrode pattern, and a second upper plug on the lower plug, the second upper plug being spaced apart from the first upper plug.


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