The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 17, 2015

Filed:

Apr. 09, 2014
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Stephen P. Ayotte, Bristol, VT (US);

Sebastien S. Quesnel, Quebec, CA;

Glen E. Richard, Burlington, VT (US);

Timothy D. Sullivan, Underhill, VT (US);

Timothy M. Sullivan, Essex, VT (US);

Assignee:

GlobalFoundries, Inc., Grand Cayman, KY;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 24/13 (2013.01); H01L 24/81 (2013.01); H01L 2224/10156 (2013.01); H01L 2224/10175 (2013.01); H01L 2224/13022 (2013.01); H01L 2224/13099 (2013.01); H01L 2224/81222 (2013.01); H01L 2224/81815 (2013.01); H01L 2924/01022 (2013.01); H01L 2924/01026 (2013.01); H01L 2924/01027 (2013.01); H01L 2924/01028 (2013.01); H01L 2924/01073 (2013.01); H01L 2924/01074 (2013.01); H01L 2924/04941 (2013.01); H01L 2924/04953 (2013.01); H01L 2924/14 (2013.01);
Abstract

A method of applying inductive heating to join an integrated circuit chip to an electrical substrate using solder bumps including applying a magnetic field to a magnetic liner in thermal contact with a solder bump on the integrated circuit chip. The magnetic field causes Joule heating in the magnetic liner sufficient to melt the solder bump, which has a lower portion embedded in a first dielectric layer and an upper portion at least partially embedded in a second dielectric layer. The lower portion is in electrical contact with a conductive pad, the first dielectric layer is above the conductive pad and the second dielectric layer is on top of the first dielectric layer. The duration of application of the magnetic field is controlled to achieve a joining temperature that is approximately halfway between the storage and operating temperatures of the integrated circuit chip.


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