The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 17, 2015

Filed:

Feb. 25, 2014
Applicant:

Samsung Electronics Co., Ltd., Gyeonggi-do, KR;

Inventors:

Kyol Park, Daejeon, KR;

Yunhyeok Im, Gyeonggi-do, KR;

Eon Soo Jang, Gyeonggi-do, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Suwon-Si, Gyeonggi-Do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/34 (2006.01); H01L 23/16 (2006.01); H01L 23/31 (2006.01); H01L 23/427 (2006.01); H01L 23/433 (2006.01); H01L 25/065 (2006.01); H01L 23/38 (2006.01);
U.S. Cl.
CPC ...
H01L 23/16 (2013.01); H01L 23/3128 (2013.01); H01L 23/4275 (2013.01); H01L 23/4334 (2013.01); H01L 25/0657 (2013.01); H01L 23/38 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01); H01L 2924/15311 (2013.01);
Abstract

A semiconductor package includes a substrate. A lower semiconductor chip is disposed above the substrate. An upper semiconductor chip is disposed on the lower semiconductor chip. A top surface of the lower semiconductor chip at an end of the lower semiconductor chip is exposed. A heat slug disposed above the upper semiconductor chip. A molding layer is disposed between the substrate and the heat slug. The molding layer is configured to seal the lower semiconductor chip and the upper semiconductor chip. An upper spacer is disposed between the lower semiconductor chip and the heat slug. The upper spacer is disposed on the exposed surface of the lower semiconductor chip.


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