The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 17, 2015

Filed:

Sep. 07, 2012
Applicants:

Olivier Thomas, Revel, FR;

Jerome Mazurier, Cestas, FR;

Nicolas Planes, La Terrasse, FR;

Olivier Weber, Grenoble, FR;

Inventors:

Olivier Thomas, Revel, FR;

Jerome Mazurier, Cestas, FR;

Nicolas Planes, La Terrasse, FR;

Olivier Weber, Grenoble, FR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/70 (2006.01); H01L 21/84 (2006.01); H01L 27/11 (2006.01); H01L 27/12 (2006.01); H01L 27/105 (2006.01); H01L 21/00 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
H01L 21/84 (2013.01); H01L 27/1052 (2013.01); H01L 27/1104 (2013.01); H01L 27/1203 (2013.01); H01L 21/823892 (2013.01); H01L 27/0928 (2013.01); H01L 29/78648 (2013.01);
Abstract

An integrated circuit on a semiconductor substrate has logic gates comprising FDSOI-type transistors made on said substrate, including at least one first transistor comprising a gate with a first work function, and including a transistor comprising a second work function, a memory including memory cells, each memory cell comprising FDSOI type transistors, including at least one third nMOS transistor with a gate presenting a third work function, the third transistor comprising a buried insulating layer and a ground plane at least one fourth pMOS transistor with a gate presenting said third work function, the fourth transistor comprising a buried insulating layer and a ground plane, the ground planes of the third and fourth transistors being made in a same well separating these ground planes from said substrate.


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