The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 17, 2015

Filed:

Oct. 24, 2014
Applicant:

Qualcomm Mems Technologies, Inc., San Diego, CA (US);

Inventors:

Jon Bradley Lasiter, Stockton, CA (US);

Ravindra V. Shenoy, Dublin, CA (US);

Donald William Kidwell, Los Gatos, CA (US);

Victor Louis Arockiaraj Pushparaj, Sunnyvale, CA (US);

Kwan-yu Lai, San Jose, CA (US);

Ana Rangelova Londergan, Santa Clara, CA (US);

Assignee:

QUALCOMM MEMS Technologies, Inc., San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/044 (2006.01); H01G 4/06 (2006.01); H01L 23/498 (2006.01); H01L 27/12 (2006.01); H01L 49/02 (2006.01); H01L 23/15 (2006.01); H01G 4/008 (2006.01); H01G 4/30 (2006.01); H05K 1/03 (2006.01); H05K 1/11 (2006.01); H05K 1/18 (2006.01); G02B 26/00 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01G 4/06 (2013.01); H01G 4/008 (2013.01); H01G 4/30 (2013.01); H01L 23/15 (2013.01); H01L 23/49827 (2013.01); H01L 27/12 (2013.01); H01L 28/60 (2013.01); H01L 28/90 (2013.01); H05K 1/0306 (2013.01); H05K 1/115 (2013.01); H05K 1/182 (2013.01); G02B 26/001 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 2224/131 (2013.01); H01L 2224/16225 (2013.01); H01L 2924/10253 (2013.01); H01L 2924/1461 (2013.01); H01L 2924/15311 (2013.01); Y10T 29/49124 (2015.01);
Abstract

This disclosure provides systems, methods, and apparatus for metal-insulator-metal capacitors on glass substrates. In one aspect, an apparatus may include a glass substrate, with the glass substrate defining at least one via in the glass substrate. A first electrode layer may be disposed over surfaces of the glass substrate, including surfaces of the at least one via. A dielectric layer may be disposed on the first electrode layer. A second electrode layer may be disposed on the dielectric layer, with the dielectric layer electrically isolating the first electrode layer from the second electrode layer.


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