The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 17, 2015
Filed:
Sep. 12, 2014
Applicant:
Fujitsu Semiconductor Limited, Yokohama-shi, Kanagawa, JP;
Inventors:
Assignee:
FUJITSU SEMICONDUCTOR LIMITED, Yokohama, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/22 (2006.01); G11C 5/06 (2006.01); G06F 11/10 (2006.01); G06F 11/07 (2006.01); G06F 11/08 (2006.01); G06F 11/00 (2006.01); G06F 12/00 (2006.01); H03M 13/11 (2006.01); G11C 11/56 (2006.01); H03M 13/09 (2006.01); H03M 13/19 (2006.01);
U.S. Cl.
CPC ...
G11C 11/2275 (2013.01); G11C 11/221 (2013.01); G11C 11/22 (2013.01); G11C 11/5657 (2013.01); H03M 13/09 (2013.01); H03M 13/118 (2013.01); H03M 13/1148 (2013.01); H03M 13/19 (2013.01);
Abstract
A ferroelectric memory device includes a memory array including a plurality of ferroelectric memory cells, a code generating circuit configured to multiply write data and a parity generator matrix to generate check bits, thereby producing a Hamming code having information bits and the check bits arranged therein, the information bits being the write data, and a driver circuit configured to write the Hamming code to the memory array, wherein the parity generator matrix has a plurality of rows, and a number of '1's in each of the rows is an even number.