The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 17, 2015
Filed:
Aug. 03, 2012
Applicants:
Joerg Appenzeller, West Lafayette, IN (US);
Saptarshi Das, West Lafayette, IN (US);
Inventors:
Joerg Appenzeller, West Lafayette, IN (US);
Saptarshi Das, West Lafayette, IN (US);
Assignee:
PURDUE RESEARCH FOUNDATION, West Lafayette, IN (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/22 (2006.01); B82Y 10/00 (2011.01); H01L 21/28 (2006.01); H01L 29/51 (2006.01); H01L 29/66 (2006.01); H01L 27/115 (2006.01); H01L 29/06 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
G11C 11/22 (2013.01); B82Y 10/00 (2013.01); H01L 21/28291 (2013.01); H01L 27/1159 (2013.01); H01L 29/0669 (2013.01); H01L 29/516 (2013.01); H01L 29/6684 (2013.01); H01L 29/78391 (2014.09);
Abstract
Illustrative embodiments provide a FETRAM that is significantly improved over the operation of conventional FeRAM technology. In accordance with at least one disclosed embodiment, a CMOS-processing compatible memory cell provides an architecture enabling a non-destructive read out operation using organic ferroelectric PVDF-TrFE as the memory storage unit and silicon nanowire as the memory read out unit.