The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 17, 2015
Filed:
May. 19, 2014
Reecha Jajodia, Noida, IN;
Gaurav Goyal, Noida, IN;
Ateet Mishra, Delhi, IN;
FREESCALE SEMICONDUCTOR, INC., Austin, TX (US);
Abstract
A scan flip-flop for generating an output signal based on a first input signal, a clock signal, a test input signal, a Launch On Shift (LOS) signal, a test enable signal, and a reset signal includes a logic circuit, a multiplexer and a flip-flop circuit. The logic circuit receives an inverted clock signal, the test enable signal, a intermediate test enable signal, and the LOS signal, and generates an intermediate output signal that is an inherent LOS scan enable signal. The multiplexer receives the test input signal and the intermediate output signal, and outputs the test input signal. The flip-flop circuit receives the test input signal as a second input signal, the clock signal, and the reset signal, and generates the output signal.