The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 10, 2015

Filed:

Jan. 12, 2015
Applicant:

Analog Devices, Inc., Norwood, MA (US);

Inventors:

Stuart McCracken, Arlington, MA (US);

John Kenney, West Windsor, NJ (US);

Kimo Tam, Lincoln, MA (US);

Assignee:

Analog Devices, Inc., Norwood, MA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 7/04 (2006.01); H04L 7/00 (2006.01); H04L 7/02 (2006.01);
U.S. Cl.
CPC ...
H04L 7/042 (2013.01); H04L 7/002 (2013.01); H04L 7/0033 (2013.01); H04L 7/02 (2013.01);
Abstract

Apparatus and methods for clock and data recovery (CDR) are provided herein. In certain configurations, a first CDR circuit captures data and edge samples from a first input data stream received over a first lane. The data and edge samples are used to generate a master phase signal, which is used to control a phase of a first data sampling clock signal used for capturing the data samples. Additionally, the first CDR circuit generates a master phase error signal based on changes to the master phase signal over time, and forwards the master phase error signal to at least a second CDR circuit. The second CDR circuit processes the master phase error signal to generate a slave phase signal used to control a phase of a second data sampling clock signal used for capturing data samples from a second input data stream received over a second lane.


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