The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 10, 2015

Filed:

Jul. 11, 2014
Applicant:

SK Hynix Inc., Gyeonggi-do, KR;

Inventor:

Min-Seok Shin, Gyeonggi-do, KR;

Assignee:

Sk Hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/34 (2006.01); H03K 21/02 (2006.01); H04N 5/3745 (2011.01); H04N 5/369 (2011.01); H03K 21/38 (2006.01); H03K 23/50 (2006.01);
U.S. Cl.
CPC ...
H03K 21/023 (2013.01); H03K 21/026 (2013.01); H03M 1/34 (2013.01); H04N 5/3698 (2013.01); H04N 5/37455 (2013.01); H03K 21/38 (2013.01); H03K 23/50 (2013.01);
Abstract

A double data rate (DDR) counter includes a first control block suitable for toggling a counter clock according to a count mode signal and a previous state value of a sampling block; a second control block suitable for determining whether to toggle a clock signal inputted to a counting block corresponding to an (LSB+1) bit or higher; a third control block suitable for determining an enable period of the counting block; the sampling block suitable for sampling a state of the clock signal and outputting an LSB value, when an input signal transits; and the counting block suitable for performing counting according to output signals of the second and third control blocks and outputting a counter output signal having the (LSB+1) bit or higher.


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