The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 10, 2015

Filed:

Jan. 22, 2010
Applicant:

Il-sug Chung, Lyngby, DK;

Inventor:

Il-Sug Chung, Lyngby, DK;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01S 5/183 (2006.01); H01S 5/10 (2006.01); H01S 5/02 (2006.01); H01S 5/026 (2006.01); H01S 5/30 (2006.01);
U.S. Cl.
CPC ...
H01S 5/10 (2013.01); H01S 5/021 (2013.01); H01S 5/026 (2013.01); H01S 5/0215 (2013.01); H01S 5/105 (2013.01); H01S 5/1032 (2013.01); H01S 5/1838 (2013.01); H01S 5/18311 (2013.01); H01S 5/18341 (2013.01); H01S 5/18366 (2013.01); H01S 5/3095 (2013.01);
Abstract

The present invention provides a light source () for light circuits on a silicon platform (). A vertical laser cavity is formed by a gain region () arranged between a top mirror () and a bottom grating-mirror () in a grating region () in a silicon layer () on a substrate. A waveguide () for receiving light from the grating region () is formed within or to be connected to the grating region, and functions as an 5 output coupler for the VCL. Thereby, vertical lasing modes () are coupled to lateral in-plane modes () of the in-plane waveguide formed in the silicon layer, and light can be provided to e.g. photonic circuits on a SOI or CMOS substrate in the silicon.


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