The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 10, 2015

Filed:

Dec. 22, 2014
Applicant:

Melexis Technologies NV, Tessenderlo, BE;

Inventors:

Ben Maes, Lommel, BE;

Carl Van Buggenhout, Aalst, BE;

Appolonius Jacobus Van Der Wiel, Duisberg, BE;

Assignee:

MELEXIS TECHNOLOGIES NV, Tessenderlo, BE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 31/09 (2006.01); H01L 33/34 (2010.01); G01J 5/02 (2006.01); G01J 5/12 (2006.01); H01L 27/146 (2006.01); G01J 5/20 (2006.01); H01L 31/18 (2006.01);
U.S. Cl.
CPC ...
H01L 31/09 (2013.01); G01J 5/02 (2013.01); G01J 5/12 (2013.01); G01J 5/20 (2013.01); H01L 27/14669 (2013.01); H01L 27/14683 (2013.01); H01L 31/18 (2013.01);
Abstract

The invention relates to an infrared thermal sensor comprising a substrate having a cavity, a cavity bottom wall formed by a continuous substrate surface. The sensor comprises a membrane adapted for receiving heat from incident infrared radiation, a beam suspending the membrane, and a thermocouple. This membrane comprises openings extending through the membrane for facilitating the passage of an anisotropic etchant for etching the cavity during manufacture. Each opening has a cross-section with a length to width ratio of at least 4. The width direction of respectively a first and a second set of openings is oriented according to respectively a first crystallographic orientation and a second crystallographic orientation, these orientations corresponding to different directions lying in loosely packed crystal lattice faces of the semiconductor substrate.


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