The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 10, 2015
Filed:
Dec. 09, 2013
Applicant:
Micrel, Inc., San Jose, CA (US);
Inventor:
David Raymond Zinn, San Jose, CA (US);
Assignee:
Micrel, Inc., San Jose, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 29/10 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7802 (2013.01); H01L 29/105 (2013.01); H01L 29/66712 (2013.01);
Abstract
A planar vertical DMOS transistor uses a conductive spacer structure formed on the sides of a dielectric structure as the gate of the transistor. The planar vertical DMOS transistor with a conductive spacer gate structure reduces the parasitic gate-to-bulk or gate-to-drain overlap capacitance by eliminating the conductive gate material that is formed above the bulk of the semiconductor layer. Meanwhile, the desired distance between the body regions formed on opposing sides of the conductive spacer gate structure is maintained.