The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 10, 2015

Filed:

Jul. 31, 2014
Applicant:

Chung Hua University, Hsinchu, TW;

Inventor:

Jium Ming Lin, Hsinchu, TW;

Assignee:

CHUNG HUA UNIVERSITY, Hsinchu, TW;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/73 (2006.01); H01L 29/739 (2006.01); H01L 29/66 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7393 (2013.01); H01L 21/76877 (2013.01); H01L 21/76883 (2013.01); H01L 21/76898 (2013.01); H01L 29/66325 (2013.01);
Abstract

A power semiconductor device comprises a substrate, a first electrode, a conductive layer, at least one electrical connecting element, a plurality of doped semiconductor layers, an insulating layer, and a second electrode. The first electrode is formed on a surface of the substrate. The conductive layer is formed on another surface of the substrate. The electrical connecting element is formed through the substrate and electrically connects the first electrode and the conductive layer. The doped semiconductor layers are stacked on the conductive layer. The upper most semiconductor layer comprises two doped sub-regions. The insulating layer is formed on the plurality of doped semiconductor layers. The second electrode is formed on the insulating layer and at least extends on an area between the doped sub-regions.


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