The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 10, 2015

Filed:

Jun. 25, 2013
Applicant:

Cree, Inc., Durham, NC (US);

Inventors:

Sei-Hyung Ryu, Cary, NC (US);

Craig Capell, Hillsborough, NC (US);

Charlotte Jonas, Morrisville, NC (US);

David Grider, Wake Forest, NC (US);

Assignee:

Cree, Inc., Durham, NC (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/092 (2006.01); H01L 27/098 (2006.01); H01L 29/16 (2006.01); H01L 29/78 (2006.01); H01L 21/8234 (2006.01); H01L 21/8238 (2006.01); H01L 27/088 (2006.01); H01L 27/12 (2006.01); H01L 21/82 (2006.01);
U.S. Cl.
CPC ...
H01L 29/1608 (2013.01); H01L 21/823487 (2013.01); H01L 21/823885 (2013.01); H01L 27/088 (2013.01); H01L 27/098 (2013.01); H01L 27/0922 (2013.01); H01L 27/1207 (2013.01); H01L 29/7802 (2013.01); H01L 21/8213 (2013.01); H01L 29/7803 (2013.01);
Abstract

A vertical power transistor is monolithically packaged on a semiconductor die with gate buffer circuitry. The gate buffer circuitry is adapted to deliver a biasing voltage to a gate contact of the vertical power transistor for switching the device between an ON state and an OFF state. By monolithically packaging the gate buffer circuitry together with the vertical power transistor, parasitic inductance between the gate buffer circuitry and the gate of the vertical power transistor is minimized, thereby decreasing the switching time of the vertical power transistor and reducing switching noise.


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