The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 10, 2015

Filed:

Oct. 31, 2014
Applicants:

Young-kuk Kim, Seoul, KR;

Ki-vin Im, Seongnam-si, KR;

Han-jin Lim, Seoul, KR;

In-seak Hwang, Suwon-si, KR;

Inventors:

Young-Kuk Kim, Seoul, KR;

Ki-Vin Im, Seongnam-si, KR;

Han-Jin Lim, Seoul, KR;

In-Seak Hwang, Suwon-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 49/02 (2006.01); H01L 21/8234 (2006.01);
U.S. Cl.
CPC ...
H01L 28/60 (2013.01); H01L 21/823437 (2013.01); H01L 21/823475 (2013.01);
Abstract

A semiconductor device includes a substrate having a field area that defines active areas, gate trenches in the substrate and extending in a first direction, a buried gate in a respective gate trench, gate capping fences in a respective gate trench over a respective buried gate, the gate capping fences protruding from top surfaces of the active areas and extending in the first direction, bit line trenches in the gate capping fences, a respective bit line trench crossing the gate capping fences and extending in a second direction perpendicular to the first direction, an insulator structure on inner walls of a respective bit line trench, bit lines and bit line capping patterns stacked on the insulator structures in a respective bit line trench, contact pads self-aligned with the gate capping fences and on the substrate between the adjacent bit lines, and a lower electrode of a capacitor on a respective contact pad.


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