The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 10, 2015
Filed:
Aug. 15, 2012
Russell Carlton Mcmullan, Allen, TX (US);
Binu Kamblath Pushkarakshan, Bangalore, IN;
Subramanian J. Narayan, Bangalore, IN;
Swaminathan Sankaran, Plano, TX (US);
Keith Edmund Kunz, Bryan, TX (US);
Russell Carlton McMullan, Allen, TX (US);
Binu Kamblath Pushkarakshan, Bangalore, IN;
Subramanian J. Narayan, Bangalore, IN;
Swaminathan Sankaran, Plano, TX (US);
Keith Edmund Kunz, Bryan, TX (US);
TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US);
Abstract
A high TCR tungsten resistor on a reverse biased Schottky diode. A high TCR tungsten resistor on an unsilicided polysilicon platform geometry. A high TCR tungsten resistor between two parallel polysilicon leads on remaining contact etch stop dielectric. A high TCR tungsten resistor embedded in a intermetal dielectric layer above a lower interconnect layer and below an upper interconnect layer. A method of forming a high TCR tungsten resistor on a reverse biased Schottky diode. A method of forming high TCR tungsten resistor on an unsilicided polysilicon platform geometry. A method of forming high TCR tungsten resistor between two parallel polysilicon leads on remaining contact etch stop dielectric. A method of forming high TCR tungsten resistor embedded in a inter metal dielectric layer above a lower interconnect layer and below an upper interconnect layer.