The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 10, 2015

Filed:

May. 08, 2014
Applicant:

Inotera Memories, Inc., Taoyuan County, TW;

Inventors:

Tzung-Han Lee, Taipei, TW;

Yaw-Wen Hu, Taoyuan County, TW;

Vishnu Kumar Agarwal, Taipei, TW;

Assignee:

Inotera Memories, Inc., Taoyuan County, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 27/108 (2006.01); H01L 21/8242 (2006.01); H01L 21/331 (2006.01);
U.S. Cl.
CPC ...
H01L 27/10814 (2013.01); H01L 27/10852 (2013.01); H01L 27/10885 (2013.01);
Abstract

The instant disclosure relates to a semiconductor device which includes a semiconductor substrate, at least one patterned reinforcing layer, a plurality of lower electrodes, and a supporting layer. The at least one patterned reinforcing layer is arranged above the semiconductor substrate, wherein the at least one patterned reinforcing layer has a plurality of reinforcing structures configured to define a plurality of alignment apertures. The lower electrodes are arranged on the semiconductor substrate, wherein N of the lower electrodes pass through each of the alignment apertures, where N is an integer greater than or equal to 1. The supporting layer is arranged above the at least one patterned reinforcing layer and between the lower electrodes.


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