The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 10, 2015

Filed:

Jun. 26, 2014
Applicant:

SK Hynix Inc., Icheon, KR;

Inventors:

Hyung Ju Choi, Seoul, KR;

Jong Hyun Kim, Seoul, KR;

Assignee:

SK HYNIX INC., Icheon, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/552 (2006.01); H01L 23/60 (2006.01); H01L 23/498 (2006.01); H01L 25/065 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/60 (2013.01); H01L 23/49822 (2013.01); H01L 23/49838 (2013.01); H01L 23/552 (2013.01); H01L 24/97 (2013.01); H01L 25/065 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48145 (2013.01); H01L 2224/48227 (2013.01); H01L 2225/06562 (2013.01); H01L 2924/15184 (2013.01);
Abstract

Semiconductor packages are provided. In some embodiments, the semiconductor package includes a substrate, a first ground line including a first internal ground line disposed along edges of the substrate and a plurality of first extended ground lines between the first internal ground line and sidewalls of the substrate, a chip on the substrate, a molding member disposed on the substrate to cover the chip, and an electromagnetic interference (EMI) shielding layer covering the molding member, the EMI shielding layer extending along the sidewalls of the substrate and contacting the end portions of the plurality of first extended ground lines. The plurality of first extended ground lines include end portions that are exposed at the sidewalls of the substrate.


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