The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 10, 2015

Filed:

Nov. 20, 2012
Applicant:

Renesas Electronics Corporation, Kawasaki-shi, Kanagawa, JP;

Inventor:

Fukuo Owada, Kawasaki, JP;

Assignee:

Renesas Electronics Corporation, Kawasaki-shi, Kanagawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 5/14 (2006.01); G11C 11/21 (2006.01); G11C 14/00 (2006.01);
U.S. Cl.
CPC ...
G11C 11/21 (2013.01); G11C 14/009 (2013.01);
Abstract

A first ReRAM unit having a resistance change layer is provided between a first access transistor configuring the SRAM and a first bit line, and a second ReRAM unit having a resistance change layer is provided between a second access transistor and a second bit line. When a low potential (L=0V) is held at a first storage node and a high potential (H=1.5V) is held at a second storage node at the end of a normal operation period of the SRAM, the first ReRAM unit is set to ON state (ON), and the second ReRAM unit is set to OFF state (OFF); accordingly, the retained data of the SRAM is written in to the ReRAM units. When the SRAM returns to the normal operation again, data corresponding to the storage nodes are written back and the ReRAM units are both set to ON state (reset).


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