The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 10, 2015
Filed:
Jan. 04, 2012
Applicants:
Jang Seok Choi, Seoul, KR;
Ju-yun Jung, Hwaseong-si, KR;
Inventors:
Jang Seok Choi, Seoul, KR;
Ju-Yun Jung, Hwaseong-si, KR;
Assignee:
SAMSUNG ELECTRONICS CO., LTD., Suwon-si, Gyeonggi-do, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/02 (2006.01); H01L 25/065 (2006.01); H01L 25/18 (2006.01);
U.S. Cl.
CPC ...
G11C 5/02 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/06181 (2013.01); H01L 2224/131 (2013.01); H01L 2224/13025 (2013.01); H01L 2224/16146 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/17181 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06565 (2013.01); H01L 2924/15311 (2013.01);
Abstract
The stacked semiconductor device including a first chip, a second chip positioned on the first chip, the second chip being connected to a plurality of first penetration electrodes and including a first memory and a memory controller that are each controlled by the first chip, and a second memory positioned on the second chip and connected to a plurality of second penetration electrodes and controlled by the memory controller.