The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9183332 B1

PDF
Full Text
Expired
Date of Patent:
Nov. 10, 2015

Filed:

Apr. 11, 2014
Applicant:

Bae Systems Information and Electronic Systems Integration Inc., Nashua, NH (US);

Inventors:

Richard Ferguson, Bealeton, VA (US);

Lloyd Brown, Fredericksburg, VA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5036 (2013.01);
Abstract

A system and method for an automated way of running spice on a small portion of a design is presented. The system includes a sub-circuit netlist generation processor and an analog simulation processor. The sub-circuit netlist generation processor generates a sub-circuit netlist based, at least in part, on a HDL netlist, a parasitic capacitance database and trace rules. The sub-circuit netlist contains significantly fewer paths than the HDL netlist of an entire design so that its simulation time is much quicker. The analog simulation processor generates analog simulation results of the sub-circuit netlist based, at least in part, on dynamic inputs.


Find Patent Forward Citations

Ferguson, Richard. (2015). Method for simulation of partial vlsi asic design (U.S. Patent No. 9183332). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9183332

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…