The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 10, 2015

Filed:

Mar. 11, 2013
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Ankit Srivastava, San Diego, CA (US);

Matthew David Sienko, San Diego, CA (US);

Eugene Robert Worley, Irvine, CA (US);

Assignee:

QUALCOMM INCORPORATED, San Diego, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H02H 9/00 (2006.01); G05F 1/10 (2006.01); H01L 27/02 (2006.01); H01L 27/06 (2006.01); H02H 9/04 (2006.01); H02H 3/00 (2006.01);
U.S. Cl.
CPC ...
G05F 1/10 (2013.01); H01L 27/0274 (2013.01); H01L 27/0277 (2013.01); H01L 27/0629 (2013.01); H02H 9/041 (2013.01); H02H 9/046 (2013.01); H02H 3/006 (2013.01);
Abstract

A device includes a snapback clamp circuit configured to clamp a supply voltage in response to the supply voltage exceeding a trigger voltage level. In at least one embodiment, the snapback clamp circuit includes a clamp transistor and a programmable resistance portion that is responsive to a control signal to calibrate the trigger voltage level. Alternatively or in addition, the snapback clamp circuit may include a programmable bias device configured to calibrate the trigger voltage level by biasing a gate terminal of the clamp transistor. In another particular embodiment, a method of calibrating a snapback clamp circuit is disclosed. In another particular embodiment, a method of operating an integrated circuit is disclosed.


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