The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 03, 2015

Filed:

Oct. 07, 2014
Applicant:

Inphi Corporation, Santa Clara, CA (US);

Inventors:

Guojun Ren, Santa Clara, CA (US);

Karthik S. Gopalakrishnan, Santa Clara, CA (US);

Assignee:

Inphi Corporation, Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H04B 1/38 (2015.01); H04L 5/16 (2006.01); H04B 3/30 (2006.01); G05F 1/10 (2006.01); H04L 25/06 (2006.01);
U.S. Cl.
CPC ...
H04B 3/30 (2013.01); G05F 1/10 (2013.01); H04L 25/06 (2013.01);
Abstract

The voltage regulator device has a wide band amplifier having an input reference voltage, Vref and an input feedback voltage, Vfbk. The device has a source follower coupled to the wide band amplifier, the source follower coupled to an output of the wide band amplifier. The device has a VDD source, a regulator output, and a current source coupled to the source follower and the VDD source. The device has a low frequency path comprising a first transistor. The first transistor has a first gate, a first source, and a first drain. The first source is coupled to the VDD source. The first gate is coupled to a slow node, and the first drain is coupled to the regulator output. The low frequency path comprises a RC network, which has a capacitor, a resistor, and the slow node configured between the resistor and the capacitor. The device has a high frequency path comprising a second transistor. The second transistor has a second gate, a second source, and a second drain. The second source is coupled to the VDD source. The second gate is coupled to a fast node, and the second drain is coupled to the regulator output.


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