The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 03, 2015

Filed:

Aug. 03, 2011
Applicants:

Yao-jun Tsai, Taoyuan County, TW;

Chen-peng Hsu, Kaohsiung, TW;

Kuo-feng Lin, Taipei County, TW;

Hsun-chih Liu, Taipei County, TW;

Hung-lieh HU, Hsinchu, TW;

Chien-jen Sun, Hsinchu County, TW;

Inventors:

Yao-Jun Tsai, Taoyuan County, TW;

Chen-Peng Hsu, Kaohsiung, TW;

Kuo-Feng Lin, Taipei County, TW;

Hsun-Chih Liu, Taipei County, TW;

Hung-Lieh Hu, Hsinchu, TW;

Chien-Jen Sun, Hsinchu County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 33/00 (2010.01); H01L 33/20 (2010.01); H01L 33/44 (2010.01);
U.S. Cl.
CPC ...
H01L 33/0095 (2013.01); H01L 33/20 (2013.01); H01L 33/44 (2013.01); H01L 2933/0016 (2013.01);
Abstract

A method for fabricating a wafer-level light emitting diode structure is provided. The method includes: providing a substrate, wherein a first semiconductor layer, a light emitting layer, and a second semiconductor layer are sequentially disposed on the substrate; subjecting the first semiconductor layer, the light emitting layer, and the second semiconductor layer with a patterning process to form a first depressed portion, a second depressed portion, a stacked structure disposed on the second depressed portion and a remained first semiconductor layer disposed on the depressed portion, wherein the stacked structure comprises a patterned second semiconductor layer, a patterned emitting layer, and a patterned first semiconductor layer; forming a first electrode on the remained first semiconductor layer of the first depressed portion; and forming a second electrode correspondingly disposed on the patterned second semiconductor layer of the second depressed portion.


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