The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 03, 2015

Filed:

Sep. 08, 2011
Applicants:

Eric Alexander Garner Webster, Glasgow, GB;

Robert Kerr Henderson, Edinburgh, GB;

Inventors:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 31/107 (2006.01); H01L 27/144 (2006.01); H01L 31/0232 (2014.01); H01L 31/0236 (2006.01); H01L 31/18 (2006.01);
U.S. Cl.
CPC ...
H01L 31/107 (2013.01); H01L 27/1443 (2013.01); H01L 31/02327 (2013.01); H01L 31/02363 (2013.01); H01L 31/18 (2013.01); H01L 31/1804 (2013.01); Y02E 10/547 (2013.01);
Abstract

A single photon avalanche diode for use in a CMOS integrated circuit includes a deep n-well region formed above a p-type substrate and an n-well region formed above and in contact with the deep n-well region. A cathode contact is connected to the n-well region via a heavily doped n-type implant. A lightly doped region forms a guard ring around the n-well and deep n-well regions. A p-well region is adjacent to the lightly doped region. An anode contact is connected to the p-well region via a heavily doped p-type implant. The junction between the bottom of the deep n-well region and the substrate forms a multiplication region when an appropriate bias voltage is applied between the anode and cathode and the guard ring breakdown voltage is controlled with appropriate control of the lateral doping concentration gradient such that the breakdown voltage is higher than that of the multiplication region.


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