The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 03, 2015

Filed:

Sep. 06, 2011
Applicants:

Hidekazu Miyairi, Atsugi, JP;

Koji Dairiki, Atsugi, JP;

Shunpei Yamazaki, Setagaya, JP;

Ryo Arasawa, Isehara, JP;

Inventors:

Hidekazu Miyairi, Atsugi, JP;

Koji Dairiki, Atsugi, JP;

Shunpei Yamazaki, Setagaya, JP;

Ryo Arasawa, Isehara, JP;

Assignee:

Semiconductor Energy Laboratory Co., Ltd., Atsugi-shi, Kanagawa-ken, JP;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 29/786 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/78678 (2013.01); H01L 29/66765 (2013.01); H01L 29/78606 (2013.01); H01L 29/78648 (2013.01); H01L 29/78669 (2013.01); H01L 29/78696 (2013.01);
Abstract

Provided is a method for manufacturing a semiconductor device with fewer masks and in a simple process. A gate electrode is formed. A gate insulating film, a semiconductor film, an impurity semiconductor film, and a conductive film are stacked in this order, covering the gate electrode. A source electrode and a drain electrode are formed by processing the conductive film. A source region, a drain region, and a semiconductor layer, an upper part of a portion of which does not overlap with the source region and the drain region is removed, are formed by processing the upper part of the semiconductor film, while the impurity semiconductor film is divided. A passivation film over the gate insulating film, the semiconductor layer, the source region, the drain region, the source electrode, and the drain electrode are formed. An etching mask is formed over the passivation film. At least the passivation film and the semiconductor layer are processed to have an island shape while an opening reaching the source electrode or the drain electrode is formed, with the use of the etching mask. The etching mask is removed. A pixel electrode is formed over the gate insulating film and the passivation film.


Find Patent Forward Citations

Loading…