The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 03, 2015
Filed:
Dec. 09, 2013
Applicant:
Micrel, Inc., San Jose, CA (US);
Inventor:
David Raymond Zinn, San Jose, CA (US);
Assignee:
Micrel, Inc., San Jose, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 21/28 (2006.01); H01L 29/66 (2006.01); H01L 29/10 (2006.01); H01L 29/51 (2006.01); H01L 29/49 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7802 (2013.01); H01L 21/28035 (2013.01); H01L 21/28158 (2013.01); H01L 29/105 (2013.01); H01L 29/1095 (2013.01); H01L 29/4916 (2013.01); H01L 29/51 (2013.01); H01L 29/6656 (2013.01); H01L 29/66712 (2013.01);
Abstract
A planar vertical DMOS transistor includes a dielectric separation structure formed under the conductive gate and over the bulk of the semiconductor layer outside of the channel region of the transistor. The planar vertical DMOS transistor with a conductive gate formed over the dielectric structure reduces the parasitic gate-to-bulk or gate-to-drain overlap capacitance by increasing the separation between the conductive gate and the bulk of the semiconductor layer. Meanwhile, the desired distance between the body regions formed on opposing sides of the conductive gate is maintained.