The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 03, 2015
Filed:
May. 04, 2012
Ki-won Kim, Suwon-si, KR;
Kap Soo Yoon, Seoul, KR;
Woo Geun Lee, Yongin-si, KR;
Jin-won Lee, Cheonan-si, KR;
Se-myung Kwon, Seongnam-si, KR;
Jung Ouck Ahn, Yangyang-gun, KR;
SI Jin Kim, Seoul, KR;
Ki-Won Kim, Suwon-si, KR;
Kap Soo Yoon, Seoul, KR;
Woo Geun Lee, Yongin-si, KR;
Jin-Won Lee, Cheonan-si, KR;
Se-Myung Kwon, Seongnam-si, KR;
Jung Ouck Ahn, Yangyang-gun, KR;
Si Jin Kim, Seoul, KR;
Samsung Display Co., Ltd., Yongin-si, KR;
Abstract
A method for manufacturing a thin film transistor array panel includes forming a gate line and a gate electrode protruding from the gate line on a substrate; forming a gate insulating layer on the gate line and the gate electrode; depositing sequentially a semiconductor material and a metal material on the gate insulating layer; performing a first etching operation on the semiconductor material and the metal material using a first mask to form a semiconductor layer and a metal layer, the metal layer including a data line, a source electrode, and a drain electrode, in which the drain electrode protrudes from the data line, and the source electrode and the drain electrode having an integral shape; and performing a second etching operation on the metal layer using a second mask to divide the source electrode and the drain electrode.