The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 03, 2015
Filed:
Dec. 01, 2009
Applicant:
Hiroyuki Fujimoto, Tokyo, JP;
Inventor:
Hiroyuki Fujimoto, Tokyo, JP;
Assignee:
PS4 Luxco S.a.r.l., Luxembourg, LU;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 47/00 (2006.01); H01L 27/02 (2006.01); H01L 27/108 (2006.01); H01L 49/02 (2006.01); H01L 27/24 (2006.01); H01L 45/00 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0207 (2013.01); H01L 27/10841 (2013.01); H01L 27/10852 (2013.01); H01L 27/2454 (2013.01); H01L 27/2463 (2013.01); H01L 28/91 (2013.01); H01L 45/04 (2013.01); H01L 45/06 (2013.01); H01L 45/144 (2013.01); H01L 45/147 (2013.01);
Abstract
The invention includes: multiple bit lines bto barranged in parallel to each other at a first line pitch; multiple word lines wto warranged in parallel to each other at a second line pitch greater than the first line pitch and intersecting with bit lines bto b; and multiple capacitors. Respective center positionsof the multiple capacitors lie above the bit lines and are displaced by given distance C from the intersection of the bit line and the word line in a direction of arranging the word lines.
Fujimoto, Hiroyuki. (2015). Semiconductor device having efficient capacitor arrangement (U.S. Patent No. 9177947). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9177947
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile