The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 03, 2015

Filed:

Dec. 03, 2010
Applicant:

Bernard J. New, Carmel Valley, CA (US);

Inventor:

Bernard J. New, Carmel Valley, CA (US);

Assignee:

XILINX, INC., San Jose, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/50 (2006.01); H01L 25/16 (2006.01); H01L 23/31 (2006.01); H01L 23/48 (2006.01); H01L 23/498 (2006.01); H01L 23/528 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 25/16 (2013.01); H01L 23/3121 (2013.01); H01L 23/481 (2013.01); H01L 23/49822 (2013.01); H01L 23/528 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 24/48 (2013.01); H01L 24/73 (2013.01); H01L 24/92 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/131 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/73207 (2013.01); H01L 2224/73257 (2013.01); H01L 2224/73265 (2013.01); H01L 2224/92127 (2013.01); H01L 2224/92227 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06541 (2013.01); H01L 2924/1461 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/18161 (2013.01); H01L 2924/19041 (2013.01); H01L 2924/19042 (2013.01); H01L 2924/19104 (2013.01);
Abstract

A semiconductor device with a stacked power converter is described. In some examples, a semiconductor device includes: a first integrated circuit (IC) die having bond pads and solder bumps, the bond pads configured for wire-bonding; and a second IC die mounted on the first IC die, the second IC die having an active side and a backside opposite the active side, the second IC die including bond pads on the active side configured for wire-bonding, and solder bumps disposed on a backside opposite the active side; where the solder bumps of the first IC die are electrically and mechanically coupled to the solder bumps of the second IC die to form bump bonds.


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