The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 03, 2015

Filed:

Dec. 27, 2013
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Xiang-Zheng Bo, Plano, TX (US);

Alwin Tsao, Garland, TX (US);

Douglas T. Grider, McKinney, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 21/266 (2006.01); H01L 21/8234 (2006.01); H01L 21/265 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 21/266 (2013.01); H01L 21/26586 (2013.01); H01L 21/823412 (2013.01); H01L 29/6659 (2013.01);
Abstract

An integrated circuit containing an analog MOS transistor may be formed by implanting drain extensions with exactly four sub-implants wherein at least one sub-implant implants dopants in a substrate of the integrated circuit at a source/drain gate edge of the analog MOS transistor at a twist angle having a magnitude of 5 degrees to 40 degrees with respect to the source/drain gate edge of the analog MOS transistor, for each source/drain gate edge of the analog MOS transistor, wherein a zero twist angle sub-implant is perpendicular to the source/drain gate edge. No more than two sub-implants put the dopants in the substrate at any source/drain gate edge of the analog MOS transistor. All four sub-implants are performed at a same tilt angle. No halo implants are performed on the analog MOS transistor.


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