The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9177623 B1

PDF
Full Text
Expired
Date of Patent:
Nov. 03, 2015

Filed:

Mar. 15, 2013
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Shree Krishna Pandey, San Diego, CA (US);

Dexter T. Chun, San Diego, CA (US);

Assignee:

QUALCOMM INCORPORATED, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/10 (2006.01); G11C 7/22 (2006.01); G06F 13/16 (2006.01); G06F 13/42 (2006.01);
U.S. Cl.
CPC ...
G11C 7/227 (2013.01); G06F 1/10 (2013.01); G06F 13/1689 (2013.01); G06F 13/4243 (2013.01);
Abstract

A memory interface includes circuitry configured for applying a variable delay to a portion of a data signal and applying a variable delay to a data strobe. The delayed data strobe samples the delayed portion of the data signal. Delayed portions of the data signal are spaced away from non-delayed portions of the data signal by alternating the routing of delayed bits and non-delayed bits of the data signal. A training block determines and sets a value of the variable delay corresponding to a largest value of a number of recorded eye aperture widths.


Find Patent Forward Citations

Pandey, Shree. (2015). Memory interface offset signaling (U.S. Patent No. 9177623). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9177623

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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