Timing closure using transistor sizing in standard cells

Abstract

An approach is provided in which a design tool executes static timing analysis of an integrated circuit design using a first set of timing values corresponding to a first set of layout properties of a transistor included in a standard cell utilized by the integrated circuit design. When the design tool determines that the static timing analysis generates a timing violation within a violation budget, the design tool selects a second set of timing values of the standard cell corresponding to a second set of layout properties of the transistor. The design tool determines that re-execution of the static timing analysis using the second set of timing values resolves the timing violation and, in turn, generates mask layer data that includes the second set of layout properties.