The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 03, 2015

Filed:

Sep. 10, 2014
Applicant:

Atoptech, Inc., Santa Clara, CA (US);

Inventor:

Ping-San Tzeng, Fremont, CA (US);

Assignee:

Atoptech, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/455 (2006.01); G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
G06F 17/505 (2013.01);
Abstract

Modifying a hierarchical circuit design includes accessing hierarchical circuit data in a hierarchical circuit design comprising top level block data and lower level block data; performing timing analysis on a selected portion of the hierarchical circuit data to determine whether timing closure is achieved; and in the event that timing closure is not achieved, determining, within a top level design process, an optimization move on the selected portion of the hierarchical circuit data; wherein the selected portion of the hierarchical circuit data includes a selected portion of the top level block data and a selected portion of the lower level block data.


Find Patent Forward Citations

Tzeng, Ping-San. (2015). In-hierarchy circuit analysis and modification for circuit instances (U.S. Patent No. 9177090). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9177090

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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