The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 03, 2015
Filed:
May. 02, 2014
Amit Kumar Dey, Noida, IN;
Himanshu Mangal, Agra, IN;
Kulbhushan Misri, Gurgaon, IN;
Amit Roy, Noida, IN;
Vijay Tayal, Noida, IN;
Chetan Verma, Noida, IN;
Amit Kumar Dey, Noida, IN;
Himanshu Mangal, Agra, IN;
Kulbhushan Misri, Gurgaon, IN;
Amit Roy, Noida, IN;
Vijay Tayal, Noida, IN;
Chetan Verma, Noida, IN;
FREESCALE SEMICONDUCTOR, INC., Austin, TX (US);
Abstract
A clock signal generator provides a gated clock signal GCLK to trigger operation of dual-edge triggered circuits. A first detector generates, while a clock gating signal /EN is asserted, a first detector output signal that is asserted or de-asserted as a function of disjunction or conjunction respectively of the values that an input clock signal CLK and the gated clock signal GCLK had when the clock gating signal /EN transitioned. A second detector generates, while the clock gating signal /EN is de-asserted, as the value of the gated clock signal GCLK, the value CLK or its complement /CLK as a function of the first detector output signal. When the clock gating signal /EN is asserted, the second detector maintains the value that the gated clock signal GCLK had when the clock gating signal /EN transitioned from de-asserted to asserted.