The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 27, 2015

Filed:

Mar. 02, 2012
Applicants:

Prasad Srinivasa Siva Gudem, San Diego, CA (US);

Xiaoyin He, San Diego, CA (US);

Tamer Adel Kadous, San Diego, CA (US);

Li-chung Chang, Irvine, CA (US);

Inventors:

Prasad Srinivasa Siva Gudem, San Diego, CA (US);

Xiaoyin He, San Diego, CA (US);

Tamer Adel Kadous, San Diego, CA (US);

Li-Chung Chang, Irvine, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04B 1/00 (2006.01); H04B 1/525 (2015.01); H04B 7/04 (2006.01);
U.S. Cl.
CPC ...
H04B 1/0057 (2013.01); H04B 1/0064 (2013.01); H04B 1/525 (2013.01); H04B 7/0413 (2013.01);
Abstract

A wireless communication device configured for receiving a wireless multiple-input and multiple-output signal. The wireless communication device includes a first multiple-input and multiple-output carrier aggregation receiver reuse architecture. The first multiple-input and multiple-output carrier aggregation receiver reuse architecture includes a first antenna, a second antenna and a transceiver chip. The first multiple-input and multiple-output carrier aggregation receiver reuse architecture reuses a first carrier aggregation receiver path. The wireless communication device also includes a second multiple-input and multiple-output carrier aggregation receiver reuse architecture. The second multiple-input and multiple-output carrier aggregation receiver reuse architecture includes a third antenna, a fourth antenna and a receiver chip. The second multiple-input and multiple-output carrier aggregation receiver reuse architecture reuses a second carrier aggregation receiver path.


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