The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 27, 2015

Filed:

Feb. 22, 2013
Applicant:

Koninklijke Philips N.v., Eindhoven, NL;

Inventors:

Stephan Gronenborn, Eindhoven, NL;

Armand Pruijmboom, Eindhoven, NL;

Raimond Louis Dumoulin, Eindhoven, NL;

Michael Miller, Eindhoven, NL;

Assignee:

Koninklijke Philips N.V., Eindhoven, NL;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01S 5/00 (2006.01); H01S 5/42 (2006.01); H01S 5/183 (2006.01); H01S 5/40 (2006.01); H01S 5/02 (2006.01); H01S 5/022 (2006.01);
U.S. Cl.
CPC ...
H01S 5/423 (2013.01); H01S 5/005 (2013.01); H01S 5/183 (2013.01); H01S 5/4018 (2013.01); H01S 5/0216 (2013.01); H01S 5/0217 (2013.01); H01S 5/02288 (2013.01); H01S 5/4025 (2013.01);
Abstract

The invention describes a method of manufacturing a VCSEL module () comprising at least one VCSEL chip () with an upper side (U) and a lower side (L) and with a plurality of VCSEL units () on a common carrier structure (), the VCSEL units () comprising a first doped layer () of a first type facing towards the lower side (L) and a second doped layer () of a second type facing towards the upper side (U). The method comprises the steps of dividing the VCSEL chip () into a plurality of subarrays () with at least one VCSEL unit () each, electrically connecting at least some of the subarrays () in series. The invention also describes a VCSEL module () manufactured in such process.


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