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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9172132 B1

PDFFull Text
Date of Patent:
Oct. 27, 2015

Filed:

Jan. 23, 2015

Integrated antenna for rfic package applications

Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Dong G. Kam, Seoul, KR;

Duixian Liu, Scarsdale, NY (US);

Scott K. Reynolds, Amawalk, NY (US);

Assignee:

GLOBALFOUNDRIES INC, Grand Cayman, KY;

Attorney:

Tutunjian & Bitetto, P.C.

Primary Examiner:

Karl D Frech

Int. Cl.
CPC ...
G06K 19/06 (2006.01); H01Q 1/22 (2006.01); H01Q 3/30 (2006.01); H01Q 9/04 (2006.01); H01Q 9/06 (2006.01); H01Q 21/06 (2006.01); H01L 23/66 (2006.01); G06K 19/077 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01Q 1/2283 (2013.01); G06K 19/07775 (2013.01); H01L 23/66 (2013.01); H01Q 3/30 (2013.01); H01Q 9/0407 (2013.01); H01Q 9/065 (2013.01); H01Q 21/065 (2013.01); H01L 24/16 (2013.01); H01L 2223/6616 (2013.01); H01L 2223/6677 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/73253 (2013.01); H01L 2924/09701 (2013.01); H01L 2924/1421 (2013.01); H01L 2924/15321 (2013.01);
Abstract

A chip package includes a set of layers including conductive planes connected by vias. A first portion has at least one antenna, antenna ground plane, and first grounded vias. A second portion has a conductive plane parallel to the ground plane that forms an interface for connecting to at least one integrated circuit device. A third portion between the first and the second portion has a vertical transmission line that includes a signal via connecting the antenna feed line to the at least one integrated circuit and a parallel-plate mode suppression mechanism. The parallel-plate mode suppression mechanism includes a grounded reflector that forms a cage with the grounded vias around an antenna region and further includes second ground vias surrounding the signal via.

Find Patent Forward Citations

Kam, Dong. (2015). Integrated antenna for rfic package applications (U.S. Patent No. 9172132). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9172132

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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