The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 27, 2015

Filed:

Aug. 06, 2013
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Christine Sung-An Hau-Riege, Fremont, CA (US);

You-Wen Yau, San Diego, CA (US);

Kevin Patrick Caffey, Cardiff by the Sea, CA (US);

Lizabeth Ann Keser, San Diego, CA (US);

Gene Hyde McAllister, La Mesa, CA (US);

Reynante Tamunan Alvarado, San Diego, CA (US);

Steve Joseph Bezuk, Poway, CA (US);

Damion Bryan Gastelum, San Marcos, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/118 (2006.01); H01L 23/485 (2006.01); H01L 21/768 (2006.01); H01L 23/532 (2006.01); H01L 23/525 (2006.01);
U.S. Cl.
CPC ...
H01L 23/485 (2013.01); H01L 21/76841 (2013.01); H01L 21/76895 (2013.01); H01L 23/53238 (2013.01); H01L 23/53266 (2013.01); H01L 23/525 (2013.01); H01L 2224/0231 (2013.01); H01L 2224/0239 (2013.01); H01L 2224/02331 (2013.01);
Abstract

Some implementations provide a semiconductor device (e.g., die) that includes a substrate, several metal layers and dielectric layers coupled to the substrate, a pad coupled to one of the plurality of metal layers, a first metal redistribution layer coupled to the pad, and a second metal redistribution layer coupled to the first metal redistribution layer. The second metal redistribution layer includes a cobalt tungsten phosphorous material. In some implementations, the first metal redistribution layer is a copper layer. In some implementations, the semiconductor device further includes a first underbump metallization (UBM) layer and a second underbump metallization (UBM) layer.


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