The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 27, 2015

Filed:

Apr. 04, 2014
Applicant:

Mitsubishi Electric Corporation, Tokyo, JP;

Inventors:

Kiyoshi Arai, Tokyo, JP;

Osamu Usui, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/02 (2006.01); H01L 23/367 (2006.01); H01L 23/42 (2006.01); H01L 23/492 (2006.01); H01L 23/373 (2006.01); H01L 23/433 (2006.01); H01L 23/498 (2006.01); H01L 23/24 (2006.01); H01L 23/053 (2006.01);
U.S. Cl.
CPC ...
H01L 23/3675 (2013.01); H01L 23/24 (2013.01); H01L 23/3735 (2013.01); H01L 23/42 (2013.01); H01L 23/4334 (2013.01); H01L 23/492 (2013.01); H01L 23/49811 (2013.01); H01L 23/053 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/73265 (2013.01); H01L 2924/12032 (2013.01); H01L 2924/1305 (2013.01); H01L 2924/13055 (2013.01); H01L 2924/13091 (2013.01);
Abstract

A semiconductor device according to the present invention includes a base plate, an insulating layer provided on an upper surface of the base plate, a metal pattern provided on an upper surface of the insulating layer, a semiconductor element bonded to the metal pattern, and an insulating substrate disposed to be in contact with an upper surface of the semiconductor element. An end of the insulating substrate is located outside the semiconductor element in plan view. The end of the insulating substrate and the metal pattern are directly or indirectly bonded. The semiconductor element includes an electrode on the upper surface. A portion of the insulating substrate, in which the electrode on the upper surface of the semiconductor element overlaps in plan view, is provided with a through-hole.


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