The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 27, 2015
Filed:
Nov. 04, 2011
Applicant:
Masao Taguchi, Tokyo, JP;
Inventor:
Masao Taguchi, Tokyo, JP;
Assignee:
CYPRESS SEMICONDUCTOR CORPORATION, San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 8/08 (2006.01); G11C 11/56 (2006.01); G11C 13/00 (2006.01);
U.S. Cl.
CPC ...
G11C 11/5685 (2013.01); G11C 13/003 (2013.01); G11C 13/004 (2013.01); G11C 13/0007 (2013.01); G11C 13/0069 (2013.01); G11C 2013/0054 (2013.01); G11C 2013/0078 (2013.01); G11C 2213/32 (2013.01); G11C 2213/34 (2013.01); G11C 2213/72 (2013.01); G11C 2213/78 (2013.01); G11C 2213/79 (2013.01);
Abstract
A resistance changing memory array architecture includes an array of resistance changing memory unit cell arranged in rows and column, wherein at least two adjacent columns share a sense bit line, and a control line individually associated with each column, wherein a current control component within each unit cell along a respective column is coupled to a respective control line. The architecture further includes a plurality of word lines each associated with a respective row, wherein a resistance changing element associated with each unit cell along a respective row is coupled to a respective word line.