The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 27, 2015

Filed:

Jul. 09, 2013
Applicant:

Nvidia Corporation, Santa Clara, CA (US);

Inventors:

William J. Dally, Los Altos Hills, CA (US);

John W. Poulton, Chapel Hill, NC (US);

Thomas Hastings Greer, III, Chapel Hill, NC (US);

Brucek Kurdo Khailany, Austin, TX (US);

Carl Thomas Gray, Apex, NC (US);

Assignee:

NVIDIA Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 11/40 (2006.01); G11C 11/4096 (2006.01); G11C 7/10 (2006.01); H04L 25/02 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4096 (2013.01); G11C 7/1057 (2013.01); G11C 7/1069 (2013.01); H04L 25/0276 (2013.01);
Abstract

A system of interconnected chips comprising a multi-chip module (MCM) includes a first processor chip, a system function chip, and an MCM package configured to include the first processor chip and the system function chip. The first processor chip is configured to include a first ground-referenced single-ended signaling (GRS) interface circuit. The system function chip is configured to include a second GRS interface circuit. A first set of electrical traces are fabricated within the MCM package and coupled to the first GRS interface circuit and to the second GRS interface circuit. The first GRS interface circuit and second GRS interface circuit together provide a communication channel between the first processor chip and the system function chip.


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