The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 27, 2015

Filed:

Dec. 31, 2011
Applicants:

Donglin Wang, Beijing, CN;

Zijun Liu, Beijing, CN;

Xiaojun Xue, Beijing, CN;

Xing Zhang, Beijing, CN;

Zhiwei Zhang, Beijing, CN;

Shaolin Xie, Beijing, CN;

Inventors:

Donglin Wang, Beijing, CN;

Zijun Liu, Beijing, CN;

Xiaojun Xue, Beijing, CN;

Xing Zhang, Beijing, CN;

Zhiwei Zhang, Beijing, CN;

Shaolin Xie, Beijing, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/02 (2006.01); G11C 7/10 (2006.01); G06F 3/06 (2006.01); G06F 12/06 (2006.01); G11C 11/406 (2006.01); G11C 21/00 (2006.01); G06F 9/38 (2006.01);
U.S. Cl.
CPC ...
G11C 7/1072 (2013.01); G06F 3/0601 (2013.01); G06F 9/3895 (2013.01); G06F 12/02 (2013.01); G06F 12/0607 (2013.01); G11C 11/40615 (2013.01); G11C 21/00 (2013.01);
Abstract

A multi-granularity parallel storage system including a plurality of memories, a shift generator, an address increment lookup unit, an address shifter, a row address generator, and a plurality of address adders. The shift generator is configured to generate a shift value. The address increment lookup unit is configured to generate input data for the address shifter. The address shifter is configured to cyclically shift the input data rightward by Shift elements and then output the shifted data. The row address generator is configured to generate a row address RowAddr and input the generated row address RowAddr to the other input terminal of each address adder. Each address adder is configured to perform a non-sign addition of the input data at the two input terminals to obtain a read/write (R/W) address for one of the memories and input the R/W address to an address input terminal of the memory.


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