The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 27, 2015

Filed:

Aug. 29, 2013
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Azzedine Touzni, San Diego, CA (US);

Thomas Zeng, San Diego, CA (US);

Assignee:

QUALCOMM INCORPORATED, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/14 (2006.01); G06F 12/10 (2006.01); G06F 15/167 (2006.01); G06F 21/60 (2013.01); G06F 21/79 (2013.01);
U.S. Cl.
CPC ...
G06F 12/1483 (2013.01); G06F 12/1009 (2013.01); G06F 12/1475 (2013.01); G06F 15/167 (2013.01); G06F 21/606 (2013.01); G06F 21/79 (2013.01);
Abstract

A first processor and a second processor are configured to communicate secure inter-processor communications (IPCs) with each other. The first processor effects secure IPCs and non-secure IPCs using a first memory management unit (MMU) to route the secure and non-secure IPCs via a memory system. The first MMU accesses a first page table stored in the memory system to route the secure IPCs and accesses a second page table stored in the memory system to route the non-secure IPCs. The second processor effects at least secure IPCs using a second MMU to route the secure IPCs via the memory system. The second MMU accesses the second page table to route the secure IPCs.


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