The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 27, 2015

Filed:

Nov. 07, 2012
Applicant:

Oracle International Corporation, Redwood City, CA (US);

Inventors:

Paul Rotker, Harvard, MA (US);

Bikram Saha, Cupertino, CA (US);

Jason Miller, Arlington, MA (US);

Assignee:

Oracle International Corporation, Redwood Shores, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01); G06F 11/07 (2006.01); G06F 11/10 (2006.01); H04L 1/00 (2006.01);
U.S. Cl.
CPC ...
G06F 11/0745 (2013.01); G06F 11/0763 (2013.01); G06F 11/10 (2013.01); G06F 11/1008 (2013.01); G06F 11/1076 (2013.01); H04L 1/0045 (2013.01); H04L 1/0061 (2013.01);
Abstract

Systems, methods, and apparatuses for error checking are disclosed. In one embodiment, an error checking system is used on a device that has a plurality of parallel data lanes as inputs. It may be desired to provide an error checking system with sufficient resolution to detect single-bit errors, determine how many bits are in error, and/or determine which bit(s) of a parallel data lane are in error. In one embodiment, the present disclosure provides for switchable error checking through the use of a multiplexor configured to select a particular data lane for error checking. This switchable error checking may provide benefits such as low cost, low power consumption, and/or low size.


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